Adaptive level binary logic

ABSTRACT

A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

This application is the US national phase of international applicationPCT/EP01/12022 filed 17 Oct. 2001 which designated the U.S., the entirecontent of which is hereby incorporated by reference.

Interpretation of binary single ended (non-differential) logic signalsencoded in the voltage or current domain requires comparison against oneor sometimes two reference voltages. This reference voltage must bechosen such that the input signal can be interpreted with good noiseimmunity. The optimum reference or threshold level depends on what logicsignaling level definition is used by the source. A variety of signalinglevel definitions is available today in the form of signaling standards.Known standardized logic signaling level definitions include for exampleTTL, CMOS, ECL and others.

FIELD OF THE INVENTION

Smaller and smaller physical transistor dimensions in integratedcircuits require reduced supply voltages in order not to exceed fieldstrength limitations. A fairly wide range of I/O signaling standards hasbeen developed to fit the limitations of lower supply voltages. Thisvariety of I/O signal standards can lead to compatibility problems. Incircuit technologies that can operate with multiple supply voltages,different types of I/O cells can be developed. If the kinds of circuitsto be connected to the various ports of the circuit under design areknown beforehand, the right kind of I/O cells can be chosen for eachport on the circuit at design time. In some applications, one set ofport signals can be required to be able to communicate with othercircuits that don't share a single common type I/O signal levelstandard.

PRIOR ART

If each application in a circuit uses fixed connections to othercircuits, level shifting interface circuits can be placed in the pathsbetween source and destination in order to adapt the logic levels of onecircuit to the other. The type of level shifter must then be chosen tofit the I/O standards of the two circuits to be connected.

Fixed threshold input buffers are simple and straightforward to use.They are useful if the logic level on an input is known beforehand,stays constant throughout the life of the product and is the same in allapplications where the product is used. Fixed threshold binary logicinput cells are often implemented as CMOS inverters. This is a lowcomplexity, low power implementation. The threshold level is howeverdependent on the drive strength ratio between PMOS and NMOS transistors,and thus sensitive to manufacturing process variations. For legacy logicsignal standards with ample voltage swings between the logic zero andthe logic one level, noise margins were large enough to handle suchprocess variations without significant performance penalty. For newerlow voltage I/O standards, in some cases the voltage swing between logiclevels is scaled more than is manufacturing process precision and noise.Differential line receivers offer an opportunity to alleviate some ofthe tolerance problems. When used for single ended signals a referencethreshold level can be created by means with much less susceptibility toprocess variations than is the CMOS inverter P/N ratio, as described inJEDEC standard JESD 8-11. The reference threshold level is determinedwith better precision but fixed throughout the life of the product.

A slightly more flexible solution is described in patent U.S. Pat. No.5,751,166 to Shieh et al wherein is described a circuit that is able tochange the threshold level for an input signal in response to the peakvoltage of the input signal. If the peak value exceeds a limit definedby a reference voltage, the input signal is assumed to be a 5V CMOSlogic signal. As long as the input signal peak level stays below thelimit the input signal is assumed to be a TTL signal.

The peak level detector sets an RS-flip-flop that disables the peakdetector and changes the threshold level for the input buffer in thesignal path of the input signal to be optimized for 5V CMOS signals.This dual threshold input buffer does however have certain limitationsthat restrict its usefulness, including the ability to handle no: morethan two specific logic level standards (TTL and 5V CMOS in theimplementation shown in the patent) which must be chosen at design timeand cannot be altered later, and the fact that the thresholds arepredetermined by the CMOS P/N transistor drive strength ratio and thusmore sensitive to process variations.

It is the object of the present invention to overcome these and otherlimitations of the prior art.

DESCRIPTION OF THE INVENTION

The digital logic interface circuit according to an embodiment of thepresent invention makes use of a logic signal representative of a logicsignaling level definition, to determine the logic swing amplitude ofsignals from a given source adopting the same logic signaling leveldefinition. The digital logic interface circuit generates a thresholdlevel from the logic swing amplitude thus determined, and comparesdigital logic input signals against the threshold level in order todiscriminate different logic levels in the digital logic input signals.The comparison result is provided as digital interface output signalsadopting a predetermined logic signaling level definition for use bysubsequent system sections. Examples of such representative signals arethe digital input logic signals themselves, clock signals or lineencoded signals. Other examples can be mode control signals or NRZsignals.

The digital logic signal interface circuit according to this embodimentcan advantageously provide an adaptive interface between a digital logicprocessing section adopting a predetermined logic signaling leveldefinition, and other system sections which adopt another logicsignaling level definition which need not be known at design time.Advantageously, the digital logic signal interface circuit is integratedwith the digital logic processing section on the same chip to render thelatter capable of communicating with other circuits without beinglimited to a particular logic signaling level definition.

Level adaptive logic in accordance with the present invention candetermine the optimum threshold voltage for a wide variety of signalinglevel definitions. Preferably, as an advantageous embodiment it can alsosend back to the source of an input signal or other destination a signaladapted to the same logic signaling level definition as that of thesource. The logic signaling level definition can be binary or any othernumber of distinct logic levels appropriate for representing digitaldata.

According to one embodiment of the invention, there is provided acircuit which has means to receive one or more digital logic inputsignals having substantially the same logical high and logical lowvoltage levels, and to determine said logical high and logical lowvoltage levels from a representative one of said digital signals, whichmay be one of the digital logic input data signals, a clock signal, aline encoded data signal or the like. The logical signal amplitudes,e.g. logical high and logical low voltage levels in case of binarylogic, are determined by utilization of peak detectors for extractingestimates of the logic high and logic low levels of said representativesignal. Means may further be provided to determine a threshold voltageabove which a signal is considered to be a logical high, and below whicha signal is considered to be a logical low, from said estimates of saidlogic high level and said logic low level.

According to another embodiment of the invention there are providedtransition detection means for detecting transitions in the voltagelevel of said representative signal, and sampling means for sampling oneor more values of the amplitude level of said representative signal atpredetermined times after the detection of a level transition in saidrepresentative signal as detected by said transition detection means.The transition detection means may also be disposed so as todiscriminate between a positive and a negative transition in saidrepresentative signal.

According to one version of this embodiment the transition detectorcomprises a differential voltage comparator biased at a noise rejectionoffset from its equilibrium point by means of a feedback networkcreating a hysteresis for providing a positive noise rejection offset ifthe output of the differential voltage comparator is high and a negativenoise rejection offset from the equilibrium if the output of thedifferential voltage comparator is low, which combined with an inputsignal capacitively coupled to the negative input of said differentialvoltage comparator, yields a sampling trigger, whenever the input signalexhibits a transient with a slope and amplitude exceeding said noiserejection offset voltage.

The transition detector may alternatively comprise a, delay locked loopinvolving an adjustable delay line, a phase comparator and a loopfilter. In this embodiment said representative signal preferably is aperiodic clock signal. The delay line provides a phase offset ofessentially 90 degrees from said representative signal by letting thephase comparator with an equilibrium for 90 degrees phase offset controlthe delay line via the loop filter, such that the resulting delayedsignal can be used to trigger sampling.

The transition detector may alternatively comprise a PLL creating a PLLoscillator signal with a period equal to a unit time interval occurringin the representative signal, for instance half the period of saidrepresentative signal if the representative signal is periodic, bylocking the output signal from the PLL oscillator to said representativesignal with a phase frequency comparator attaining equilibrium whennon-sampling transitions of the PLL oscillator clock are essentiallycoincident with transitions of the representative signal, and samplingtransitions of the PLL oscillator clock fall essentially in the middleof the symbol intervals of the representative signal, such that theresulting signal can be used to trigger sampling.

According to another embodiment of the invention, a first one of saidsampling means is provided to sample said representative signal after apositive transition in said representative signal, and a second one ofsaid sampling means is provided to sample said representative sampleafter negative transition in said representative signal. Said first andsecond sampling means may be sample and hold circuits, and wherein thesample taken by said first sampling means is taken to be representativeof said logical high voltage level, and the sample taken by said secondsampling means is taken to be representative of said logical low voltagelevel.

Two resistive elements may be coupled between the outputs of the sampleand hold circuits in series, the voltage between the two resistors beingtaken to be representative of said threshold voltage. Advantageously thesample and hold circuits are edge triggered with a certain samplingdelay from the edge to the sampling instant, such that overshoot andother spurious effects resulting from the transition do not adverselyaffect the signaling logic level amplitude estimation. Extending thesampling time can further reduce noise and thus, can further improve thelogic level amplitude estimation accuracy. This can advantageouslyinclude processing the signal using a resistive sampling device,implementing a gated low pass filter together with a hold capacitor.

According to another embodiment of the invention there is provided acircuit which has means to receive one or more digital signals adoptingthe same logic signaling level definition such that they havesubstantially the same logical high and logical low voltage levels, andto determine a threshold voltage above which a signal is considered tobe a logical high, and below which a signal is considered to be alogical low, from a representative one of said digital signals. Thisthreshold is determined by averaging the amplitude of saidrepresentative signal over time. This can be achieved by low pass filterfor extracting the DC component of the representative signal. In thisembodiment it is preferable to use signals with a well defined dutycycle as representative signals. For example, a clock signal would besuitable.

According to another embodiment there are provided one or moretransition detection means for detecting transitions in the voltagelevel of said representative signal, and sampling means for sampling oneor more values of the voltage level of said representative signal atpredetermined times after the detection of a transition as detected by apredetermined one of said transition detection means, and a timeaveraging means and such that the samples taken by said first samplingmeans and by said second sampling means are averaged together over aperiod which is long compared to the period between transitions on saidrepresentative signal, the resulting time average signal being taken tobe representative of said threshold voltage. These first and secondsampling means may comprise first and second MOS transistors whose gatesare connected to a differentiator circuit comprising a series connectionof a resistive element and a capacitive element embodying saidtransition detection means, whose sources are connected to saidrepresentative signal and whose drains are connected to said averagingmeans. This embodiment is advantageous in that it will operatesatisfactorily even if the duty cycle of the representative signal isunknown or if the representative signal is a data signal wherein logichigh and low levels alternate at random.

Either of the embodiments heretofore discussed may advantageouslyprovide a logic high voltage rail and a logic low voltage rail bybuffering the detected logic high and logic low voltage levels extractedfrom the representative signal. This logic high voltage rail and logiclow voltage rail may further be used as power connections to one or moredigital data transmitters as a means for defining the output logic highand output logic low levels to equal the logic high and logic lowestimates extracted from the template signal. The digital datatransmitters can be embodied by buffers with rail to rail output stagesor by unity gain amplifiers each with an input selector connecting theinput of the unity gain buffer to the logic high level rail whenever thelogic signal to be output by said unity gain buffer is high and to thelogic low level rail whenever the logic signal to be output by saidunity gain buffer is low as a means for defining the output logic highand output logic low levels to equal the logic high and logic lowestimates extracted from said representative signal.

Specific embodiments of the present invention will be described in thefollowing with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows an embodiment of a digital logic interface circuitcomprising a receive and transmit circuit for binary logic signals.

FIG. 2 shows in more detail the components of a threshold and voltagecontrol circuit in the embodiment of FIG. 1;

FIG. 3 shows a further embodiment of a threshold signal generatingcircuit in a digital logic interface circuit according to the embodimentof FIG. 1.

FIG. 4 shows a yet another embodiment of a threshold signal generatingcircuit in a digital logic interface circuit according to the embodimentof FIG. 1.

FIG. 5 shows details of an embodiment of a circuit for detecting logicalhigh and logical low voltage levels.

Detailed descriptions of a few embodiments of the present invention willfollow. In the figures below analog signals with analog processing andanalog storage elements are shown for the stored quantities. The samecircuit principles can be used with digitized signals, digital signalprocessing and digital storage elements. For reasons of simplicity, inthe figures signals and parts/lines carrying the respective signals aredenoted with the same reference numerals.

FIG. 1 shows a receive and transmit circuit for binary logic signalsaccording to an embodiment of the present invention. There is providedan input for a representative signal 31, a threshold and voltage controlcircuit 2, and one or more output drivers 4 for sending digital logicoutput signals 33 to other circuits or system sections not shown in thefigure. There are further provided one or more inputs for data signals32 having logical high and logical low values similar to those of therepresentative signal 31, and an interface output driver 41, 42 for eachdata signal which provide corresponding digital interface output signals51, 52 to a digital logic circuit for processing received logic signals51, 52 providing other logic signals 53. The logic circuit block 5 shownin FIG. 1 receives and provides logic signals adopting a predeterminedlogic signaling level definition like CMOS or TTL. It can perform anykind of function or operation, either logic or analog or both. Thespecific functions of circuit 5 are not part of the present invention,nor is the invention limited to any specific features of the circuit 5.A threshold voltage determined by the threshold and voltage controlcircuit 2 is connected to the inverting inputs of the drivers 41, 42.The threshold and voltage control circuit 2 further provides positiveand negative power supply rails to the output drivers 4 such that thelogical high and low values of the digital signal at the outputs of theoutput drivers 4, correspond to the positive and negative power supplyrails voltage, respectively.

Thus in operation, the threshold and voltage control circuits 2 of thisembodiment analyses the representative signal 31 so as to determine thelogical high and logical low voltage values of said signal, and toprovide corresponding voltages as power supply rails to the outputdriver, 4 so that the output signal 33 has corresponding logical highand logical low voltages, and further the threshold voltage controlcircuit 2 analyses the representative signal 31, e.g. clock or templatesignal, so as to determine a cross-over threshold voltage, voltagesbelow which being interpreted as logical low, and voltages above whichbeing interpreted as logical high, and supplying this threshold voltageto the interface output drivers 41, 42 for use in determining thelogical values of incoming logic signals 31, 32. The interface outputdrivers 41, 42 pass the logic levels thus determined on to adestination, e.g. subsequent sections, using a predetermined logicsignaling level definition. The destination further processes thereceived logic signals and also provides other logic signals fortransmission to other destinations through the digital interfacecircuit, as indicated by the arrows-between the digital interfacecircuit and the destination, which arrows each represent one or moredigital logic signal channels. While FIG. 1 shows for reasons ofsimplicity a single output driver 4 for transmitting signals, it is tobe understood that any number of signal outputs for transmitting signalscan be provided.

A clock signal or DC balanced data signal available from the source withunknown logic levels are suitable as representative signals for thelogic levels to be used for communication. If such a signal isavailable, the threshold level for interpreting input signals can begenerated as a low pass filtered average of the template signal. Thelogic high and logic low levels can be determined by peak detectors orlevel samplers. If only ground-referenced logic families need to behandled and ground potential offsets are negligible, a low leveldetector is not needed. A fixed ground level can then be used instead ofthe logic low level estimate voltage.

In circuits that are only required to operate properly in the presenceof a clock signal or line encoded data signal from the outside signalsource, the optimum threshold level can be determined by low passfiltering. Clock signals and DC balanced line encoded data signals havean average input voltage that falls halfway between the logic levels.One such signal is selected as a template signal for sensing the logiclevels from the external source, and low pass filtered with a cutofffrequency substantially lower than the lowest frequency on the templatesignal. This produces an average of the input template signal on theoutput of the low pass filter. Using this voltage as the referencevoltage for differential line receivers for all input signals from thesame source will place the decision threshold at the optimum pointhalfway between the voltages of the two logic levels.

FIG. 2 shows in more detail the components of the threshold and voltagecontrol circuit 2 according to a first embodiment of the invention. Inaddition to the components described with reference to FIG. 1, which inFIG. 2 bear the same reference numerals as in FIG. 1, there is providedas subunits of the threshold and voltage control circuits 2, a firstpeak detector or level sampler 21, a second peak detector or levelsampler 22 and a low-pass filter 23 for determining an input signaltaken as the average of the representative signal. All three of thesesubunits 21, 22 and 23 are connected to receive the input representativesignal 31, and the first peak detector or level sampler 21 is connectedto the positive supply rail V+ of the output drivers 4 the thresholddetermining means 23 is connected to the inverting input of the outputdrivers 41, 42, and the second peak detector or level sampler 22 isconnected to the negative power supply rail V− of the output drivers 4.

In operation, the first peak detector or level sampler 21 operates so asto detect the logical high voltage value of the incoming representativesignal 31, the second peak detector or level sampler 22 operates so asto detect the logical low voltage level of the representative signal 31,and the threshold level detector 23 performs a low-pass filter averagingfunction on the representative signal 31, so as to determine a thresholdvoltage value as described above. If only ground reference logicfamilies needs to be handled and ground potential offsets arenegligable, it is possible to dispense with the low level detector. Afixed ground level can then be used instead of the logic low levelestimate voltage.

In the embodiments of the invention described with reference to FIG. 2,it is assumed that the representative signal comprises a regular clocksignal or line encoded data signal, such that the average voltage fallshalf-way between the two logic levels.

If no DC balanced representative signal is available, or if clockstopping must be supported, adaptive binary logic can be equipped withone of a couple of different input threshold optimizers to cater forthis situation. Two analog implementations will now be described, bothof which react to transients on the input data signal.

FIG. 3 shows a further embodiment of the present invention, in which thevariable threshold determining circuit 2 comprises an adaptive binarylogic circuit. According to this embodiment, the voltage thresholddetermining circuit 2 comprises a first capacitor 2324, one terminal ofwhich is connected to earth, a p-channel transistor 2322, and ann-channel transistor 2323, the gates of which are both connected to thesecond terminal of the capacitor 2324, and the sources of which areconnected to the representative signal 31. There is further provided aresistor 2321, which is connected between the representative signal 31,and the gates of said transistors 2322 and 2323. A further n-channeltransistor 2326 is provided, the gate and drain of which are coupledtogether and further coupled to the drain of said first p-channeltransistor 2322, and a second p-channel transistor 2327, the gate anddrain of which are coupled together and further coupled to the source ofsaid first n-channel transistor 2323. The sources of both secondp-channel transistor 2327 and second n-channel transistor 2326 arecoupled together and to a first terminal of a second resistor 2328, thesecond terminal of which provides the output of the voltage thresholddetection device, and is coupled to the inverting input of the interfaceoutput drivers 41 and 42. There is further provided a second capacitor2325, one terminal of which is connected to ground, and the other isconnected to the output of the voltage threshold determining circuits23. When a positive edge occurs in the representative signal a voltagedrop will occur across resistor 2321 until the voltage across thecapacitor 2334 has followed this transition of the input representativesignal. The voltage drop across resistor 2321 will thus temporarily turnthe p-channel transistor 2322 conductive, the duration of the conductivestate being determined inter alia by the resistance and capacitance,respectively, of the elements 2321 and 2324. During this conductiveperiod following a positive edge in the input representative signal, acircuit exists from the source of p-channel transistor 2322 throughn-channel transistor 2326 acting as a diode, to an integrator circuitwhich in this embodiment comprises a series connection of resistor 2328and capacitor 2325. Similarly, if a negative edge occurs in therepresentative signal at the input of circuit 2, the n-channeltransistor 2323 will temporarily turn conductive, and resulting in atemporary connection of the integrator circuit 2328, 2325 to the inputof threshold determining circuit 2 through the p-channel transistor 2327acting as a diode.

The threshold generating circuit 2 according to this embodiment can thusprovide an average depending on the low and the high signal amplitudelevels of the input representative signal, but largely independent fromthe duration of the respective logic states of the input representativesignal. The threshold generating circuit of this embodiment can,therefore, also process data signals showing a random alternation oflogic states.

This circuit has the effect of sampling the representative signal for apredetermined period after each transition. The RC circuit formed byresistor 2328 and capacitor 2325 is provided so as to average thissample signal, to provide the voltage threshold value to the interfaceoutput drivers 41, 42.

This circuit thus has the effect of maintaining a weighted average ofthe input voltage, where voltage is occurring shortly after transientson the input are weighted much higher than all those occurring in steadystate conditions.

The circuit reacts to transients exceeding the threshold voltage for oneof the two input transistors across resistor 2321. The upper path is acharging-path for the capacitor 2325 on the output, and the lowercurrent path is for discharging the output capacitor 2325. Thiscapacitor maintains a weighted average of the input voltage, wherevoltages occurring shortly after transients on the input are weightedmuch higher than are those occurring in steady state situations. Atransient of enough amplitude to overcome transistor threshold voltageswill make one of the input transistors conductive for a period of timedetermined by the RC network 2321, 2324 connected to its gate electrode.The weighted average is used as a reference for discriminating the logicstate of input signals in the interface output buffers 41, 42.

FIG. 4 shows a further embodiment of a threshold generating circuit 2.All other elements of FIG. 4 retain the numbering of the previousfigures and reference is made to the description of the previous figureswith respect to these other elements. The threshold generating circuit 2consists of two pairs of resistors 2332, 2333 and 2334, 2335,respectively, connected as potential divider circuits between a positiveand negative power supply rail. A capacitor 2331 is provided coupledbetween the input representation signal at the input of the thresholdgenerating circuit 2, and the node of the first potential dividercircuit between resistors 2332 and 2333. There is further provided acomparator 2337, the inverting input of which is connected to the nodeof the potential divider circuit between resistors 2332 and 2333, andthe non-inverting input is connected to the node between resistors 2334and 2335. A further resistor 2336 is connected between the non-invertinginput of the comparator 2337 and the output of the comparator 2337.There is further provided an inverter buffer 2342, and a first sampleand hold circuit 2339, the inputs of said inverter buffer 2342, and thetrigger input of the sample and hold circuit 2339 being connected to theoutput of the comparator 2337. A second sample and hold circuit 2338 isprovided, the trigger input of which is connected to the output of saidinverter 2342. The inputs of said first and second sample and holdcircuits 2339 and 2338 are connected to the input representative signal31. A series connection of a further resistor 2341 and a second furtherresistor 2340 is connected between the outputs of the first and thesecond sample and hold circuit 2338 and 2339. A node between theresistors 2340 and 2341 constitutes the output of the thresholdgenerating circuit 2. The outputs of the sample and hold circuits 2340,2341 can be coupled to provide positive and negative power supplyvoltages V+, V− to the output drivers 4 as described above. To this endbuffers for lowering the source impedance may be provided, which are notshown in the figure. Possible implementations of such circuits forbuffering the voltages V+, V− may include emitter followers, sourcefollowers, operational amplifiers with feedback from the output to thenegative input, and the like. All these and other buffer circuits aresuitable and well known in the art.

In operation, the differential voltage comparator 2337 of thisembodiment is biased at a noise rejection offset from its equilibriumpoint by means of the feedback network 2334, 2336, 2335 creating apositive noise rejection offset if the output of the differentialvoltage comparator 2337 is high and a negative noise rejection offsetfrom the equilibrium if the output of the differential voltagecomparator 2337 is low. Combined with an input signal capacitivelycoupled to the negative input of said differential voltage comparator2337, this yields a signal at the output of comparator 2337 whichchanges state whenever the input signal exhibits a transient with anamplitude exceeding said noise rejection offset voltage. The resultingpulses can be used as sampling pulses for determining first orderestimates of the logic high and logic low levels of the inputrepresentative signal. A threshold voltage for interpreting one or moreinput signals with properties similar to those of the inputrepresentative signal is determined by creating an average with thepotential divider comprising the resistors 2340 and 2341, of said firstorder estimates of the logic high and logic low levels of the templateinput logic signal.

The comparator 2337 generates sampling signals for sampling sample andhold circuits 2338 and 2339 that maintain first order estimates, i.e.time averages of the representative signal amplitude levels taken duringtime intervals determined by the edges occurring in the representativesignal. These first order estimates are averaged by a potential dividerformed by resistors 2340 and 2341 to create an adaptive threshold forinterpreting the input signals in the one or more interface outputbuffers 41, 42. This sampling pulse generator also reacts to transientson the inputs exceeding a certain limit value. This value is defined bythe ratio between resistors 2332 and 2333, and 2334 and 2335,respectively, and is therefore adjustable. The ratios are chosen so thatthe transient detection threshold is low enough for the lowest logiclevel to overcome these limits, but high enough for suppressing noisefrom affecting the first order estimate.

Alternatively, digital signal processing can be used for extraction ofthreshold and logic levels. The sampling frequency should be more thantwice the maximum fundamental frequency of the input representativesignal to be sure to capture both the high and the low level. If thesampling frequency is substantially higher than the maximum fundamentalsignal frequency, input data can be determined directly from the datasamples, otherwise a faster receive process is obtained by calculatingand then D/A converting a suitable threshold level for differential datareceivers 41, 42 as described above. Several signal processing functionscan be used for determining estimates of the logic high and logic lowlevels. For example, a discrimination procedure rejecting amplitudecalculations yielding signal amplitude results below a limit amplitudeas a means of stopping noise from being interpreted as the input signalduring longer periods without change of level of said digital inputsignals may be appropriate.

FIG. 5 shows a further embodiment of the threshold generating circuit 2,comprising means for detecting the logical high and logical low voltagelevels V+ and V−, respectively. Again with respect to all other elementsin FIG. 5 retaining the same numbering as in other figures, reference ismade to the description of these elements in the context of the otherfigures.

The threshold generating circuit 2 according to this embodimentcomprises a positive edge triggered pulse generator 211, a sample andhold circuit 212, and a buffer 213. The pulse generator 211 is triggeredby the input representative signal, and preferably by the output of anoutput driver 42 providing a replica of the input representative signal,as shown in FIG. 5. The sample and hold circuit input is connected tothe input representative signal 31, and the trigger of the sample andhold circuit is connected to the output of the pulse generator 211. Theoutput of the sample and hold circuit 212 is connected to thenon-inverting input of the buffer 213, the output of which provides thepositive power supply rail for the output drivers 4. Similarly, thelogic low voltage level detection circuit 22 comprises a falling edgetriggered pulse generation circuit 221, a sample and hold circuit 222and a buffer 223, where the input of the pulse generator 221 isconnected to receive said input representative signal, or preferably, toreceive a signal from the output 52 of an output driver 42, whichcarries a replica of the input representative signal 31. The triggerinput of the sample and hold circuit 222 is connected to the output ofthe pulse generator 221, the input of the sample and hold circuit 222 isconnected to the input representative signal 31, and the output of thesample and hold circuit is connected to the input of the buffer 223, theoutput of which is connected to the negative voltage supply rail for theoutput drivers 4. A further resistor 2341 is, connected between theoutput of the first buffer 213 and the output of the thresholdgenerating circuit 2, and a second further resistor 2340 is connectedbetween the output of said second buffer 223 and the output of saidthreshold generating circuit 23.

The pulse generated by the pulse generators 211 and 221 is shortcompared to the positive or negative pulse time of the inputrepresentative signal. Since the pulse generator 211 is triggered on arising edge and the pulse generator 221 is generated on a falling edge,the sample and hold circuits 212 and 222 will be triggered to sample thelogical high and logical low voltage levels, respectively. The outputsof the sample and hold circuits are buffered to provide a power sourceof the appropriate level adapted to the levels found by the thresholdgenerating circuit in the input representative signal 31.

The digital logic interface circuit as described above, translatessignal amplitude levels of digital logic input signals to those usedinside a destination circuit for performing logic signal processing onthe received logic signals, thus implementing adaptive level logic byproviding a level adapted replica of the digital input logic signals. Inthese embodiments of FIG. 5, the replica signal triggers' two pulsegenerators creating sampling pulses shorter in duration than the minimumbit interval or pulse time of the template signal. The first pulsegenerator fires on positive edges of the template replica, and the otherpulse generator fires on negative edges of the template replica. Theoutput signal from the first pulse generator gates a sample-and-holdcircuit, which stores an estimate of the logic high level of thetemplate signal. The output signal from the second pulse generator gatesa sample-and-hold circuit, which stores an estimate of the logic lowlevel of the template signal. The logic high and logic low estimates arebuffered and used as power rails or output level references for thedigital signal drivers 4 outputting signals to be sent to thedestination as from where the input template signal is originating, orto other system sections. In this manner, sent signals will use the samelogic high and logic low voltages as signals originating from thatblock.

Depending on the demands of the application where adaptive binary logicis used, modifications and additions to the concepts described above canbe implemented without leaving the scope of the invention. An alternateform of pulse generator can be used if signals with significantovershoot or ringing must be handled. Some protection against upsets byringing can be offered by using long enough sampling pulses. Preferablythe sampling pulse should be long enough for any ringing to have diedout before the end of the tracking period. If the range of frequenciesto be handled is too wide to meet this requirement with a fixed samplingpulse width, a clock tracking PLL or DLL based pulse generator can beused in order to adjust the sampling instant in proportion to thefrequency or bit rate used. If a clock signal is available, a DLL basedsolution is preferred. The input clock signal is delayed with anadjustable delay line and the output of the delay line is input to aphase comparator together with the input clock signal. In an ordinaryDLL manner the phase comparator controls the delay of the delay line viaa loop filter, and the DLL is set up such that equilibrium is reachedwhen the input and output signals of the delay line are 90 degrees outof phase. In this way sampling edges (or track and hold endpoints) canconveniently be generated to match for example a quarter period of theinput template clock signal.

If no clock signal is available, a clock signal can be extracted from adata signal by means of a clock recovery PLL. Such a clock signal can beused for sampling the high and low logic levels of a data signal takenas an input representative signal. The signal that is used for clockextraction should suffice also for logic level sampling. The logic levelsamples can be binned into the high and low category by pre or postsampling categorization as described above.

While specific embodiments of the present invention have been describedin detail above, the present invention should not be construed to belimited thereto. A large variety of modifications will become apparentto those skilled in the art from the description of the invention, whichmodifications fall within the scope of the invention described in theclaims.

1. A digital logic signal interface circuit (1) for adaptively receivingand discriminating at least one digital logic input signal (31,32)taking signal amplitude levels each representative of one of a pluralityof different logic levels in accordance with a logic signallingdefinition, said digital logic signal interface circuit (1) comprising acircuit (2) adapted to receive a digital logic representative signal(31) taking signal amplitude levels representative of said logicsignalling definition, for generating a threshold signal (Vth) dependingon a logic swing amplitude occurring in said digital logicrepresentative signal (31), said threshold signal generating circuit (2)comprising an amplitude detector circuit (21,22) for detecting at leastone signal amplitude level repetitively taken by said digital logicrepresentative signal (31), and for providing at least one amplitudedetection signal (V+, V−) which is indicative of said at least onedetected signal amplitude level; a logic level discriminator circuit(41,42) adapted to receive said at least one digital logic input signal(31,32) and said threshold signal (Vth), and adapted to provide for eachof said at least one digital logic input signal a corresponding digitalinterface output signal (51,52) taking one of a plurality ofpredetermined signal amplitude levels indicative of a result ofcomparing said digital logic input signal (31,32) amplitude level tosaid threshold signal (Vth); characterized by at least one output buffercircuit (4) adapted to receive a digital logic interface input signal(53) and to generate in accordance therewith, a digital logic outputsignal (33) taking signal amplitude levels each representative of one ofsaid plurality of different logic levels; said output buffer circuit (4)being coupled to receive said at least one amplitude detection signal(V+, V−) from said amplitude detector circuit (21,22) and to generatesaid signal amplitude levels in accordance with said at least oneamplitude detection signal, such that said digital logic output signal(33) can adaptively meet said logic signalling definition of saiddigital logic input signal (31,33).
 2. The digital logic signalinterface circuit according to claim 1, wherein said threshold signalgenerating circuit (2) comprises a threshold generator circuit(2340,2341) for generating said threshold signal (Vth) depending on saidat least one amplitude detection signal (V+, V−).
 3. The digital logicsignal interface circuit (1) according to claim 2, wherein saidamplitude detector circuit (21,22) comprises a peak detector circuit forextracting at least one peak amplitude level in said digital logicrepresentative signal (31).
 4. The digital logic signal interfacecircuit according to claim 2, wherein said amplitude detector circuit(2321,2324; 2331-2333; 211,221) comprises an edge detector circuit fordetecting the occurrence of edges in said digital logic representativesignal, and a sampling circuit (2322,2323; 2338,2339; 212,222) forsampling the signal amplitude of said digital logic representativesignal (31) at times controlled by said edge detector circuit.
 5. Thedigital logic signal interface circuit (1) according to claim 4, whereinsaid sampling circuit (2322,2323,212,222) is adapted to sample thesignal amplitude of said digital logic representative signal during anextended sampling time interval, and to generate said amplitudedetection signal (V+, V−) based on low pass filtering the section ofsaid digital logic representative signal (31) taken during said extendedsampling time interval.
 6. The digital logic signal interface circuit(1) according to claim 5, wherein said sampling circuit(2322,2323,2328,2325) is adapted to generate said amplitude detectionsignal based on a time average of or low pass filter operation performedon the signal amplitude of said digital logic representative signal (31)section taken during said extended sampling time interval.
 7. Thedigital logic signal interface circuit according to claim 5, whereinsaid extended sampling time interval has a duration in the order of halfthe data clock period of said digital logic representative signal (31).8. The digital logic signal interface circuit according to claim 5,wherein said extended sampling time interval extends from one edgeoccurring in said digital logic representative signal (31) to the nextedge in said digital logic representative signal (31).
 9. The digitallogic signal interface circuit according to claim 4, comprising asampling delay circuit for delaying sampling of said digital logicrepresentative signal (31) by a predetermined amount after theoccurrence of an edge in said digital logic representative signal (31).10. The digital logic signal interface circuit according to claim 1wherein said amplitude detector circuit (21,22) is adapted to detect ahigh signal amplitude level and furthermore, a low signal amplitudelevel taken by said digital logic representative signal (31), and toprovide corresponding high amplitude and low amplitude detection signals(V+, V−), respectively; and said threshold generator circuit (2)comprises a level averaging circuit (23,2340,2341) coupled to provide anaverage of said high amplitude and low amplitude detection signals assaid threshold signal.
 11. The digital logic signal interface circuit(1) according to claim 1, wherein said amplitude detector circuit isadapted to detect a high signal amplitude level taken by said digitallogic representative signal, and to provide a corresponding highamplitude detection signal; and said threshold generator circuit (2)comprises a signal level divider circuit for dividing the signal levelof said high amplitude detection signal by about two, in order toprovide said threshold signal.
 12. The digital logic interface circuit(1) according to claim 1, wherein said threshold signal generatingcircuit (2) comprises a low pass filter circuit (23) for filtering saiddigital logic representative signal (31) and extracting a DC componenttherein as said threshold signal.
 13. The digital logic interfacecircuit (1) according to claim 12, wherein said low pass filter circuit(23) comprises a sample and hold circuit for sampling said digital logicrepresentative signal, an analog to digital converter for converting thesamples provided by said sample and hold circuit into a digitalrepresentation, a digital filter circuit for processing the digitalsamples obtained from said sample and hold circuit, and a digital toanalog converter for converting the digital output of said digitalfilter into said threshold signal (Vth).
 14. The digital logic interfacecircuit (1) according to claim 1, wherein said circuit (2) forgenerating a threshold signal is coupled with said logic leveldiscriminator circuit (41,42) to receive said digital logic input signalreceived by said logic level discriminator circuit as saidrepresentative signal (31).
 15. The digital logic interface circuit (1)according to claim 1, wherein said circuit for providing a thresholdsignal (Vth) is coupled to receive a digital logic signal (31) differentfrom said at least one digital logic input signal (32) as said digitallogic representative signal.
 16. The digital logic interface circuit (1)according to claim 15, wherein said digital logic representative signal(31) is a clock signal and said at least one digital logic input signalis a data signal.
 17. The digital logic interface circuit (1) accordingto claim 1, wherein said logic level discriminator circuit (41,42) isadapted to provide said at least one digital interface output signal(51,52) at a first one of said predetermined signal levels when saidcorresponding digital logic input signal (31,32) has a signal levelabove said threshold signal level (Vth), and at a second one of saidpredetermined signal levels when said corresponding digital logic inputsignal (31,32) has a signal level below said threshold signal level(Vth).
 18. A digital logic circuit (1,5) having at least one input(31,32) for receiving at least one digital logic input signal takingsignal amplitude levels each corresponding to one of a plurality ofdifferent logic levels, and at least one output (33) for outputting atleast one digital logic output signal, furthermore having a digitallogic processing circuit (5) for performing logical operations on saidat least one digital logic input signal, and for providing at least onelogic output signal (53), said,digital logic circuit comprising adigital logic interface circuit (1) according to claim 1, coupledbetween said input (31,32) and output (33) on the one hand and coupledon the other hand to receive from said logic processing circuit (5) saidat least one digital logic interface input signal (53) and to provide tosaid logic processing circuit said at least one digital logic interlaceoutput signal (51,52).